1. Field of the Invention
The present invention relates to a failure-analyzing semiconductor device having memory cells and a method of manufacturing a semiconductor device using the failure-analyzing semiconductor device. More specifically, the present invention relates to a failure-analyzing semiconductor device adapted to monitor the process, yield and reliability in a factory on a regular basis and a method of manufacturing a semiconductor device using the failure-analyzing semiconductor device.
2. Description of the Related Art
Conventionally, in a production line for semiconductor devices, failure-analyzing LSIs (large-scale integrated circuits) have been produced on a regular basis in addition to LSI products for sale. These LSIs are used to improve the yield in the semiconductor device production line or to test the reliability on behalf of products.
For example, in the manufacture of SRAMs (static random access memories), failure-analyzing LSIs (hereinafter referred to as SRAM-TEG (test element group)) each having an SRAM cell array and a test pattern formed have been used.
With the use of the SRAM-TEG, when failures have occurred, a memory test can be made to identify defective cells. Also, the SRAM-TEG, being simple in structure, allows ease of identification of defective regions and analysis of causes. The introduction of an FBM (fail bit map) system has made the identification and analysis of defective cells and regions still easier.
The FBM is a system which represents memory cells in rows and columns according to their physical arrangement and displays defective cells and non-defective cells. In the FBM, defective cells are divided into a number of failure categories according to their arrangement. The failure categories are patterns of arrangement of defective bits (defective cells) detected by the FRB system. The failure categories vary according to interconnection structures of SRAMs.
A conventional failure-analyzing LSI will be described with some accompanying drawings.
FIG. 1A is a plan view of interconnection patterns of the conventional failure-analyzing LSI. FIG. 1B schematically shows, in a sectional view, the structure of the failure-analyzing LSI.
As shown in FIG. 1B, a semiconductor substrate 51 has diffused regions (active regions) 52 formed therein. On the opposite sides of each diffused region are formed two memory cells (not shown). Memory cells corresponding to eight bits are formed for four diffused regions 52.
Over the semiconductor substrate 51 are formed sequentially first-level interconnect patterns (not shown) and a second-level interconnect patterns (in the drawing, a bit line pattern 53A is shown) with an insulating film interposed therebetween. The bit line pattern 53A is connected to the diffused regions 52 through via holes 54. FIG. 1B is a sectional view of the bit line pattern 53A of the failure-analyzing LSI along the column direction.
As the second-level interconnect patterns, as shown in FIG. 1A, /bit line patterns 53B and reference-potential line patterns 53C are formed in addition to the bit line patterns 53A. The bit line patterns 53A and the /bit line patterns 53B are interconnections which are supplied with different potentials each of which is the inverse of the other. The bit line patterns 53A and the /bit line patterns 53B are supplied with a write signal or read signal in a read operation or write operation. The reference potential line patterns 53C are supplied with a reference potential.
In such a failure-analyzing LSI, failures which occur in the bit line patterns 53A, the /bit line patterns 53B and the reference potential line patterns 53C are detected by the FBM. For example, in the event of a short circuit between each pattern, the FBM becomes as depicted in FIG. 2.
Next, another conventional failure-analyzing LSI will be described.
FIG. 3A is a plan view of interconnection patterns of the conventional failure-analyzing LSI. FIG. 3B schematically shows, in a sectional view, the structure of the failure-analyzing LSI.
As shown in FIG. 3B, as in the aforementioned failure-analyzing LSI, the semiconductor substrate 51 has diffused regions (active regions) 52 formed therein. Memory cells corresponding to eight bits are formed for four diffused regions 52.
Over the semiconductor substrate 51 are formed sequentially first-level interconnect patterns (not shown), second-level interconnect patterns (in the drawing, the bit line pattern 53A is shown) and third-level interconnect patterns (in the drawing, a bit line pattern 55A is shown) with an insulating film interposed between each interconnect pattern. The bit line pattern 53A is connected to the diffused regions 52 through via holes 56. The bit line pattern 55A is connected to the bit line pattern 53A through via holes 57.
FIG. 3A shows only the second- and third-level interconnect patterns. As the second-level interconnect patterns, /bit line patterns 53B and reference-potential line patterns 53C are formed in addition to the bit line patterns 53A. As the third-level interconnect patterns, /bit line patterns 55B are formed in addition to the bit line patterns 55A.
The bit line patterns 53A and the /bit line patterns 53B are interconnections which are supplied with different potentials each of which is the inverse of the other. The bit line patterns 53A and the /bit line patterns 53B are supplied with a write signal or read signal in a read operation or write operation. The reference potential line patterns 53C are supplied with a reference potential. Likewise, the bit line patterns 55A and the /bit line patterns 55B are interconnections which are supplied with different potentials each of which is the inverse of the other. The bit line patterns 55A and the /bit line patterns 55B are supplied with a write signal or read signal in a read operation or write operation. The reference potential line patterns 53C are supplied with a reference potential.
In such a failure-analyzing LSI, failures which occur in the second-level line patterns 53A, 53B and 53C and the third-level line patterns 55A and 55B are detected by the FBM. For example, in the event of a short circuit between the second-level line patterns or the third-level line patters, the FBM will show the same failure category as depicted in FIG. 2.
However, the failure-analyzing LSI shown in FIG. 1B has a problem that since the density of interconnections, such as the bit line patterns 53A, the /bit line patterns 53B and the reference potential line patterns 53C, in the memory cell array is low and there is little minimum space between each interconnection, the rate of detection of a short circuit between each interconnection is low.
In the failure-analyzing LSI shown in FIG. 3B, the failure category detected by the FBM in the event that the second-level bit line patterns 53A and 53B are short-circuited is the same as in the event that the third-level bit line patterns 55A and 55B are short-circuited. For this reason, a layer in which a failure has occurred cannot be identified. That is, even with different defective regions or different causes of failure, the FBM indicates the same failure category, making it difficult to identify defective regions or causes of failure. Therefore, physical analysis of defective regions is required.
In LSIs, multilevel interconnections have been increasingly used. In failure-analyzing LSIs (SRAM-TEG and the like) as well, multilevel interconnections are being adopted accordingly. This results in an increase in the probability of different defective regions or different causes of failure being indicated as the same failure category.
It is an object of the present invention to provide a semiconductor device which saves the necessity of physical analysis of defective regions and allows the time required for failure analysis to be reduced and the rate of failure detection to be improved.
It is another object of the present invention to provide a method of manufacturing a semiconductor device using a failure-analyzing semiconductor device which allows failures which occur in semiconductor devices to be reduced.
According to a first aspect of the present invention, there is provided a failure-analyzing semiconductor device comprising: a semiconductor substrate formed with memory cells for storing information; a first digitated interconnection formed above the semiconductor substrate and connected to the memory cells; and a second digitated interconnection formed above the semiconductor substrate and connected to the memory cells, the second digitated interconnection being formed at the same level as the first digitated interconnection with a predetermined space therebetween.
According to a second aspect of the present invention, there is provided a failure-analyzing semiconductor device comprising: a semiconductor substrate formed with memory cells for storing information; a first interconnection formed above the semiconductor substrate and connected to the memory cells; a second interconnection formed above the semiconductor substrate and connected to the memory cells, the second interconnection being formed at the same level as the first interconnection with a predetermined space therebetween; a third interconnection formed above the first interconnection and connected to the memory cells, the third interconnection being formed adjacent to the second interconnection; and a fourth interconnection formed at the same level as the third interconnection with a predetermined space therebetween and connected to the memory cells.
According to a third aspect of the present invention, there is provided a semiconductor device comprising: a first semiconductor substrate formed with memory cells for storing information and adapted for a product; a second semiconductor substrate formed with memory cells and adapted for failure analysis, the second semiconductor substrate having first and second digitated interconnections formed at the same level above the second semiconductor substrate and connected to the memory cells in the second semiconductor substrate, the first and second interconnections being arranged so that the fingers of each interconnection being interleaved with those of the other with a predetermined space therebetween.
According to a fourth aspect of the present invention, there is provided a semiconductor device comprising: a first semiconductor substrate formed with memory cells for storing information and adapted for a product; a second semiconductor substrate formed with memory cells and adapted for failure analysis, the second semiconductor substrate having a first interconnection formed above the second semiconductor substrate and connected to the memory cells; a second interconnection formed at the same level as the first interconnection with a predetermined space therebetween and connected to the memory cells; a third interconnection formed above the first interconnection and connected to the memory cells, the third interconnection being formed adjacent to the second interconnection; and a fourth interconnection formed at the same level as the third interconnection with a predetermined space therebetween and connected to the memory cells.
According to a fifth embodiment of the present invention, there is provided a semiconductor device manufacturing method using a failure-analyzing semiconductor device comprising: a first circuit formation step of forming a first electronic circuit on a first wafer using a production line; a first wafer processing step of processing the first wafer having the first electronic circuit formed in the first circuit formation step so that it can be shipped; a second circuit formation step of forming a testing electronic circuit on a testing wafer using the production line; a failure analyzing step of making failure analysis using the testing electronic circuit formed on the testing wafer; a tuning step of tuning the production line on the basis of the analyses in the failure analyzing step; a third circuit formation step of forming a second electronic circuit having at least a circuit diagram identical to that of the first electronic circuit on a second wafer using the production line subjected to tuning; and a second wafer processing step of processing the second wafer having the second electronic circuit formed in the third circuit formation step so that it can be shipped.
In the semiconductor device according to each of the first to fourth aspects, the minimum space portion is formed between the first and second interconnections or the third and fourth interconnections. The first and second interconnections or the third and fourth interconnections are formed so that the minimum space portion therebetween is increases. Thereby, the rate of detecting failure which may occur between the interconnections can be improved and the time required for failure analysis can be reduced.
In the semiconductor device manufacturing method using a failure-analyzing semiconductor device according to the fifth aspect of the present invention, failure analysis is made using a testing electronic circuit formed on a testing wafer and the production line is tuned on the basis of the analyzes of failure. Thereby, failures in semiconductor devices formed in the second wafer can be reduced.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.